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Tuesday, August 6, 2013

PPT On Microprocessor And it's Architecture


Microprocessor And it's Architecture Presentation Transcript:
1.The Microprocessor and its Architecture

2.Intel Architecture

3.Programming Model

4.General-Purpose Registers
The top portion of the programming model contains the general purpose registers: EAX, EBX, ECX, EDX, EBP, ESI, and EDI. 
These registers, although general in nature, each have special purposes and names.
EAX – Accumulator (as general as they come) used also as AX, AH, and AL
EBX – Base Index often used to address memory data (BX, BH, and BL)

5.ECX – count used in shifts and loops (CX, CH, and CL)
EDX – data used in multiply and divide (DX, DH, and DL)
EBP – base point used to address stack data (BP)
ESI – source index addresses memory data (SI)
EDI – destination index addresses memory data (DI)

6.Special-Purpose Registers
The special purpose register each have specific tasks and are ESP, EIP, and EFLAGS
ESP – address stack data used in functions (procedures) and temporary storage (SP)
EIP – addresses the next instruction in a program (IP)
EFLAGS – indicates conditions of the microprocessor (FLAGS)


8.The Flags
C – holds a carry or a borrow
P – the parity flag (little use today)
A – auxiliary flag used with DAA and DAS
Z – zero
S – sign
O – Overflow
D – direction (used with string instructions)
I – interrupt (interrupt on/off)
T – trap flag (trace on/off)

9.Newer Flag Bits
IOPL – I/O privilege level for Windows
NT – nested task
RF – resume flag
VM – virtual mode
AC – alignment check
VIF – virtual interrupt (copy of interrupt flag)
VIP – virtual interrupt pending
ID = CPUID instruction available

10.Segment Register  
The segment registers are: CS (code), DS (data), ES (extra), SS (stack), FS, and GS.
Segment registers address a section of memory in a program.  A segment is either 64K in length (real mode) or up to 4G in length (protected mode).
All code (programs) reside in the code segment.

11.Default Segments for Offset address

12.Real Mode Memory Addressing
Real mode memory is the first 1M of the memory system.
All real mode addresses are a combination of a segment address plus an offset address.
The segment address (16-bits) is appended with a 0H or 00002 to form a 20-bit address.  (or multiplied by 10H)
The effective address is this 20-bit segment address plus a 16-bit offset address.

Default 16-bit addresses are programs in CS, stack data in SS, and most other data in a program in DS.
Default 32-bit addresses are programs in CS, stack data in SS and most other data in DS.
What’s the difference?  16-bit addresses use offset addresses in BX, SI, DI, BP, or an offset numeric value.  32-bit addresses use offset addresses in EAX, EBX, ECX, EDX, EBP, EDI, ESI or a numeric value.
Programs resides in segment CS addressed by IP/EIP
Stack data resides segment SS addressed by SP/ESP

14.Effective Address Calculations
EA = segment x 10H plus offset
        (a)   10023 = 10000 + 0023
        (b)    ABC34 = AAF00 + 0134
        (c)    21FF0 = 12000 + FFF0
Example (a) contained 1000 in the segment register, example (b) contained a AAF0 in the segment register, and example (c) contained a 1200 in the segment register.  

Segment and offset addressing allows for easy and efficient relocation of code and data.
To relocate code or data only the segment number needs to be changed.  For example, if an instruction appears at offset address 0002 the segment address does not matter because if it changes so does the effective address of he instruction.

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