PowerPoint Presentation On Advance Processor

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Advance Processor Presentation Transcript:

1. ABOUT COMPANY
•ARM is short for Advanced Risc Machines Ltd. •Worlds leading semiconductor IP suplier •Income forms of royalties, development tools (HW & SW) and Services •Founded 1990, owned by Acorn, Apple and VLSI Technologies –1993 Nippon Investment and Finance became ARM’sfourth investor •over 15 billion arm based chips shipped to date Headquarter at Cambridge U.K, design centers in U.S, France, India

2. About ARM
•ARM is one of the most licensed and thus widespread processor cores in the world –ARM chips sold three times more chips than PowerPC consortium •Used especially in portable devices due to low power consumptionand reasonable performance (MIPS / watt) •Available as a macrocell(fixed, ready made layout) or as synthesisable(-S) version SUN and ARM announced long-term collaboration agreement for Direct hardware implementation of Java VM

3. ARM processors
are used extensively in consumer electronics , including PDA, mobile phones, digital media and music players, hand-held game consoles, calculators and computer peripherals such as hard drives and routers. ARM licensees include Alcatel-Lucent, Apple Inc., Atmel, Broadcom, Cirrus Logic, Digital Equipment Corporation, Freescale, Intel(through DEC), LG, Marvell Technology Group, NEC, NVIDIA, NXP (previously Philips), Oki, Qualcomm, Samsung, Sharp, ST Microelectronics, Symbios Logic, Texas Instruments, VLSI Technology, Yamaha and ZiiLABS.

4. •32-bit RISC-processor core (32-bit instructions) •37 pieces of 32-bit integer registers (16 available) •Pipelined (3 stages) •Von Neuman-type bus structure (ARM7) •8 / 16 / 32 -bit data types 7 modes of operation •Simple structure -> good speed / power consumption ratio

 5. modes of operation: –
User (usr):Normal program execution state –FIQ (fiq):Data transfer state (fast irq, DMA-type transfer) –IRQ (iqr):Used for general interrupt services –Supervisor (svc):Protected mode for operating system support –Abort mode (abt):Selected when data or instruction fetch is aborted –System (sys):Operating system ‘privilege’-mode for user –Undefined (und):Selected when undefined instruction is fetched

6. •Register structure depends on mode of operation •16 pieces of 32-bit integer registers R0 -R15 are available in ARM-mode (usr, user) •R0 -R12 are general purpose registers •R13 is Stack Pointer (SP) •R14 is subroutine Link Register –Holds the value of R15 when BL-instruction is executed •R15 is Program Counter (PC) –Bits 1 and 0 are zeroes in ARM-state (32-bit addressing) •R16 is state register (CPSR, Current Program Status Register)

7. •Fully 32-bit instruction set in native operating mode –32-bit long instruction word •All instructions are conditional –Normal execution with condition AL (always) •For a RISC-processor, the instruction set is quite diverse with different addressing modes •Instruction word length 32-bits •36 instruction formats •In conditional operations one of the 14 available conditions is selected •For example, instruction known usually as BNZ in ARM is NE (Z-flag clear) conditioned branch-instruction

8. •The most used ARM-version •TDMI = (?) –Thumb instruction set –Debug-interface –Multiplier (hardware) –Interrupt (fast interrupts)

9. •T (Thumb)-extension shrinks the ARM instruction set to 16-bit word length -> 35-40% saving in amount of memory compared to 32-bit instruction set •Extension enables simpler and significantly cheaper realization of processor system. Instructions take only half of memory than with 32-bit instruction set without significant decrease in performance or increase in code size. •Extension is made to instruction decoder at the processor pipeline •Registers are preserved as 32-bit but only half of them are available

10. Thanks.