PPT On Chip Interconnect Structure for Giga-Scale Integration VLSI ICs
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Chip Interconnect Structure for Giga-Scale Integration VLSI ICs Presentation Transcript:
1.Novel On Chip Interconnect Structure for Giga-Scale Integration VLSI ICs
2.Introduction
It can be observed that the speed of the 1 mm long
interconnect
1.0µm -> 100 nm technology, 20 times faster
6 times slower than the MOSFET.
For 35 nm technology, the interconnect is almost 1000 times slower than the MOSFET.
Hence, the performance of future giga-scale integration (GSI) systems will be severely restricted by
interconnect performance.
3.GSI
The increase in transistor count increases the number of interconnects that need to be routed.
There is an increase in the number of metal levels with each new technology generation.
Interconnect design techniques that will reduce the impact of multilevel interconnect networks on the power, performance and cost of the entire system.
4.Itanium family containing 1.72 billion transistors wiring of billion transistors increases interconnect scaling the distributed resistance-capacitance product. (wire length)
5.SOLUTIONS TO THE INTERCONNECT PROBLEM
Low-K Dielectric And Low Resistivity Interconnect Material-- carbon doped silicon dioxide
Repeater Insertion
Wave-Pipelining(proposed)
6.Types of Interconnections
7.WPM
8.Interconnect design techniques will reduce the impact of interconnect networks on the
power
Performance
cost of the entire system.
Wave-Pipelined Multiplexed (WPM) Routing
9.Circuit diagram of WPM Routing Technique
10.WPM Nets
The sources and the sinks of the two nets should satisfy the source-sink proximity
The nets should have a length greater than a threshold interconnect length. Here the threshold length is determined based on the total area occupied by all the cells. Assuming a square placement for all the cells, the threshold length is assumed to be half the edge size.
Download
Chip Interconnect Structure for Giga-Scale Integration VLSI ICs Presentation Transcript:
1.Novel On Chip Interconnect Structure for Giga-Scale Integration VLSI ICs
2.Introduction
It can be observed that the speed of the 1 mm long
interconnect
1.0µm -> 100 nm technology, 20 times faster
6 times slower than the MOSFET.
For 35 nm technology, the interconnect is almost 1000 times slower than the MOSFET.
Hence, the performance of future giga-scale integration (GSI) systems will be severely restricted by
interconnect performance.
3.GSI
The increase in transistor count increases the number of interconnects that need to be routed.
There is an increase in the number of metal levels with each new technology generation.
Interconnect design techniques that will reduce the impact of multilevel interconnect networks on the power, performance and cost of the entire system.
4.Itanium family containing 1.72 billion transistors wiring of billion transistors increases interconnect scaling the distributed resistance-capacitance product. (wire length)
5.SOLUTIONS TO THE INTERCONNECT PROBLEM
Low-K Dielectric And Low Resistivity Interconnect Material-- carbon doped silicon dioxide
Repeater Insertion
Wave-Pipelining(proposed)
6.Types of Interconnections
7.WPM
8.Interconnect design techniques will reduce the impact of interconnect networks on the
power
Performance
cost of the entire system.
Wave-Pipelined Multiplexed (WPM) Routing
9.Circuit diagram of WPM Routing Technique
10.WPM Nets
The sources and the sinks of the two nets should satisfy the source-sink proximity
The nets should have a length greater than a threshold interconnect length. Here the threshold length is determined based on the total area occupied by all the cells. Assuming a square placement for all the cells, the threshold length is assumed to be half the edge size.
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